High data reliability, high speed of memory access, and reduced chip size are features that are demanded from semiconductor memory.
A dynamic random access memory (DRAM), which is a typical semiconductor memory device, stores information by charges accumulated in cell capacitors, and, therefore, the information is lost unless refresh operations are periodically carried out. In addition to normal memory cell retention characteristics, as the density of DRAM cells has increased, certain access patters may further reduce retention time, thereby leading to data becoming corrupted. Such a problem has been exposed in DRAM devices, by repeatedly accessing (i.e., hammering) a row of memory, commonly referred to as a row hammer. A row hammer causes adjacent rows of memory to become susceptible to accelerated loss of data, as compared with a normal access operation of the memory. Some conventional solutions have been implemented to detect a likely row hammer of a target row, and initiate a refresh of rows that are adjacent to the target row. As row hammer attacks become more sophisticated, such as employing a higher frequency decoy attack to mask lower frequency targeted attack, conventional row hammer detection circuitry is susceptible to overlooking these more sophisticated attacks.